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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 32: Block RAM and FIFO Switching Characteristics (Cont’d)
Speed Grade
Symbol
Description
1.0V
0.9V
Units
-3
-2/-2L
-1
-1M
-2L
F MAX_FIFO
F MAX_ECC
FIFO in all modes without ECC
Block RAM and FIFO in ECC
configuration
601.32
484.26
543.77
430.85
458.09
351.12
458.09
351.12
372.44
254.13
MHz
MHz
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
The timing report shows all of these parameters as T RCKO_DO .
T RCKO_DOR includes T RCKO_DOW , T RCKO_DOPR , and T RCKO_DOPW as well as the B port equivalent timing parameters.
These parameters also apply to synchronous FIFO with DO_REG = 0.
T RCKO_DO includes T RCKO_DOP as well as the B port equivalent timing parameters.
These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1.
T RCKO_FLAGS includes the following parameters: T RCKO_AEMPTY , T RCKO_AFULL , T RCKO_EMPTY , T RCKO_FULL , T RCKO_RDERR , T RCKO_WRERR.
T RCKO_POINTERS includes both T RCKO_RDCOUNT and T RCKO_WRCOUNT.
The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted) . Otherwise, block RAM data corruption is possible.
These parameters include both A and B inputs as well as the parity inputs of A and B.
T RCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
RDEN and WREN must be held Low prior to and during reset. The FIFO reset must be asserted for at least five positive clock edges of the
slowest clock (WRCLK or RDCLK).
DS182 (v2.8) March 4, 2014
Product Specification
www.xilinx.com
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